In order to achieve a relatively high frequency operation for an integrated circuit, there will be provided on that integrated circuit clock circuitry. This clock circuitry will operate at some base reference frequency that is typically defined by a crystal time base. However, to obtain higher operating speeds, higher clock frequencies are required than are provided with the base timing circuitry. To facilitate this, clock multipliers are utilized. For example, there are situations where certain circuitry on the integrated circuit is not capable of operating at the integer multiplication factor. This is due to the fact that there is some component on a functional block on the circuit that, due to processing limitations, etc., do not allow the overall integrated circuit to function at the highest clock operating speed, although the clock portion of the integrated circuit can operate at that frequency. However, there may be a maximum operating speed or frequency at which the functional circuitry will operate that is not an integer multiplication factor of the base timing of the clock. Rather than redesign the multiplier circuit, the full multiplication of the clock is performed and then a fractional divide is made to that maximized clock frequency. For example, if a base timing clock circuit operated on a crystal and provided a 25 MHz base clock, which was then multiplied to 100 MHz by a 4× multiplier, it may be that the functional circuitry or processing circuitry associated with the rest of the integrated circuit can only operate at ⅔ of the 100 MHz operating frequency or 66.67 MHz. Therefore, a fractional divide circuit of ⅔ would be required.